As illustrated in the equivalent circuit diagram depicted in FIG. 4, integrated circuit comparators typically include: a bias system generating a defined current bias to each transistor; an input differential pair—either complementary metal oxide semiconductor (CMOS) or bipolar junction transistors—that, for a given overdrive voltage V(ov)=(V(inp)−V(inn)) generate a differential current given by I(ov)=gm*V(ov), where gm is the transconductance of the input differential pair at the steady-state operating point V(ov)=0 volts (V); a gain stage node ngain converting the current I(ov) to (in the CMOS case) a voltage gain and having a transition speed depending on the overdrive current I(ov) available, the voltage excursion required between the high and low levels at the ngain node, and the capacitive load at the ngain node, including any Miller capacitance from the comparator's output stage; and a gain stage assuring a given slew rate at the comparator output out.
Additional non-ideal effects for most comparators include random and systematic offset of the input differential pair, the common mode rejection ratio of the input differential pair, and power supply rejection and propagation delay dependence on the power supply voltage. For example, a comparator's propagation delay will typically be related to the applied overdrive voltage V(ov), with a lower overdrive voltage resulting in a longer propagation delay.
Some techniques currently proposed or employed to reduce the comparator's propagation delay include reducing the capacitive loading of the comparator's ngain node, increasing the transconductance gm of the input differential pair by, for instance, increasing the bias current applied to that input differential pair, and reducing the voltage excursion of the ngain node to a minimum.
There is, therefore, a need in the art for alternatives for reducing an integrated circuit comparator's propagation delay while maintaining or reducing power consumption by the comparator.